Overview

Pipelining involves multiple tasks operating simultaneously using different resources. helping with the throughput of the entire load (not the latency of a single task! — each still take same amount of time).

Some possible delays include stalling for dependencies and the pipeline rate being limited by the slowest stage.

MIPS Pipeline Stages

There are 5 execution stages:

• IF: instruction fetch
• ID: Instruction decode & Register read
• EX: Execute an operation/ Calculate an address
• MEM: Access an operand in data memory
• WB: Write back the result in register

and the idea is that each execution stage takes 1 clock cycle with the general flow of data from 1 stage to the next. Previously when introduced, all stages are non-pipelined and occur in 1 clock cycle. The clock cycles will be different.

• Recap of each stage

note that PC and register file write back is slightly different

Visualising how the pipeline looks in MIPS

Datapath

We will need to make some changes to the datapath for pipelining.